FIG. 1 is a cross-sectional view of a portion of a prior art insulated gate thyristor 10 described in U.S. Pat. No. 7,705,368, incorporated herein by reference. An NPNP semiconductor layered structure is formed. In FIG. 1, there is a PNP transistor formed by a p+ substrate 12, an n− epitaxial (epi) layer 14, and a p-well 16. There is also an NPN transistor formed by the layer 14, the p-well 16, and an n+ layer 18. A bottom anode electrode 20 contacts the substrate 12, and a cathode electrode 22 contacts the n+ layer 18. Trenches 24, coated with an oxide layer 25, contain a conductive gate material 26 (forming interconnected vertical gate regions) which is contacted by a gate electrode 28. The p-well 16 surrounds the gate structure, and the n− epi layer 14 extends to the surface around the p-well 16.
When the anode electrode 20 is forward biased with respect to the cathode electrode 22, but without a sufficiently positive gate bias, there is no current flow, since the product of the betas (gains) of the PNP and NPN transistors is less than one.
When the gate is forward biased, electrons from the n+ layer 18 become the majority carriers along the sidewalls and below the bottom of the trenches 24 in an inversion layer, causing the effective width of the NPN base (the portion of the p-well 16 below the trenches 24) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This results in “breakover,” when holes are injected into the lightly doped n− epi layer 14 and electrons are injected into the p-well 16 to fully turn on the thyristor. Accordingly, the gate bias initiates the turn-on, and the full turn-on is accomplished by the current flow through the NPN and PNP transistors.
When the gate bias is removed, the thyristor turns off.
Although not described in U.S. Pat. No. 7,705,368, the identical gate structure and p-well 16 shown in FIG. 1 may be repeated as an array of cells across the thyristor, and the various components may be connected in parallel so each cell conducts a small portion of the total current. The array (or matrix) of cells includes cells designed to be inner cells and cells designed to be edge cells.
FIG. 2 is a cross-section of a portion of an edge cell 32 of a thyristor described in Applicant's U.S. patent publication US 2013/0115739, incorporated herein by reference, filed on Oct. 10, 2012 and published on May 9, 2013. The principle of operation of the cell 32 is the same as that of FIG. 1. The edge cell 32 includes a p-well 36, insulated gate regions 38, an oxide layer 39 within the trenches, an n+ layer 40 between the gate regions 38, a cathode electrode 42, a gate electrode 44, and dielectric regions 46 patterned to insulate the metal from certain areas. The cells are formed in an n− epi layer 50 grown over a silicon p+ substrate 52. An anode electrode 54 contacts the substrate 52.
The thyristor is formed of many cells in a two-dimensional matrix of parallel-connected cells. FIG. 3 is a simplified top down view of two edge cells 32, where the edge cells form a perimeter around the inner cells and are substantially identical to the inner cells. The gate region of one inner cell continues across the cell boundary to the next inner cell or to an edge cell, so that, effectively, there is only one large gate in the thyristor. In one embodiment, there are between four to nine parallel trenches per cell. The continuation of the matrix in two-dimensions is represented by the ellipses 55. The rightmost gate region 56 in FIG. 2 serves as an electrical connector between the gate electrode 44 and the other gate regions 38 in the thyristor. The gate region 56 is not surrounded by the n+ layer 40.
As shown in FIG. 2, the edge cells, unlike the “inner” cells, are next to p+ guard rings 57 and 58 formed in the n− epi layer 50, which reduce electric field crowding near the edges of the die to improve the breakdown voltage of the thyristor.
Since the cells are discontinuous at the edges, there are no emitters (n+ layer 40) in the p-base (p-well 36) on one side of the edge cells 32. Therefore, the edge cells 32 experience a different electrical environment compared to the “inner” cells. One difference is that, when the thyristor is forward biased and the gate voltage is below the threshold for turning on the thyristor, a relatively large number of holes, injected into the n− epi layer 50 (the base of the PNP transistor) from the p+ substrate 52, drift into the right side of the p-well 36. These holes drift to the nearest n+ region 60 next to gate 38A where they can contribute to the current flow and undesirably lower the breakover voltage of the thyristor. This breakover voltage is the forward voltage at which the thyristor turns on without any gate turn-on voltage. Ideally, the thyristor turn-on is solely controlled by the gate voltage and not the magnitude of the voltage applied to the anode and cathode electrodes. Therefore, having a high breakover voltage is desirable.
What is needed is an improvement of the thyristor shown in FIG. 1 or FIG. 2 which does not experience a decrease in breakover voltage due to the edge cells.